1. Field of the Invention
The present invention relates to a computer system employing a pipeline control.
2. Description of the Related Art
FIG. 10 is a block diagram showing a conventional computer system. As shown in FIG. 10, a conventional computer system is composed of an instruction fetch block 1 (hereinafter, it is referred to as IFB), a decode block 4 (hereinafter, it is referred as DECB), and an execution block 7 (hereinafter, it is referred as EXB). A clock signal CLK is input to each block. The IFB 1 includes an instruction register 2 for storing a fetched instruction, and an output 3 of the instruction register 2 is inputted to the DECB 4. The DECB 4 includes a decode signal register 5 for storing a decoded signal of output 3 of the instruction register 2, and an output 6 of the decoded signal register 5 is inputted to the EXB 7. In the EXB 7, ALUA and ALUB are inputted as input data, and ALUCNT is inputted as a control data to an arithmetic logic unit 20 (hereinafter, it is referred as ALU). An output 23 of the ALU 20 is inputted to an execution (EX) register 30 for storing an execution result. The signals ALUA, ALUB, ALUCNT are determined by the output 6 of the decode signal register 5.
A pipeline processing flow of the computer system having the above mentioned configuration is described with a timing chart. FIG. 11 is a timing chart describing the work flow of the conventional computer system. As shown In the FIG. 11, an instruction fetch processing of the instruction 1 is performed in the period “a”.
Next, when the period “b” starts, the instruction code of the instruction 1 is stored in the instruction register 2. In addition, at the period “b”, the IFB 1 fetches the instruction 2, and the decoded signal of the instruction 1 is generated by the DECB 4 by decoding the output 3 of the instruction register 2.
Next, when the period “c” starts, the decoded signal of the instruction 1 is stored in the decode signal register 5. In addition, at the period “c”, the IFB 1 fetches the instruction 3, the decoded signal of the instruction 2 is generated by the DECB 4, and the data processing regarding the specified operand data is executed by the EXB 7 according to the decoded signal of the instruction 1 outputted from the decode signal register 5.
Next, when the period “d” starts, the execution result of the instruction 1 is stored in the EX register 30. In addition, at the period “d”, the IFB 1 fetches the instruction 4, the decoded signal of the instruction 3 is generated by the DECB 4, and the data processing is executed by the EXB 7 according to the decoded signal of the instruction 2.
As shown above, at the period “a”, the instruction 1 is fetched from the memory, and at the period “d”, the execution result is stored into the EX register 30. This series of processing is executed as the pipeline processing, and the instructions are processed one after another.
The processing execution time by the EXB 7 depends on the data value to be executed. Therefore, the case requiring the longest execution time in the assumed processing will be a bottle-neck in processing for pipeline acceleration. The case requiring the longest execution time is called a “critical path”. The critical path depends on the data value to be executed. For example, in the case of an addition or subtraction processing, the number of the carry shift caused in the processing becoming maximum will be a critical path.
In the conventional computer system, in order to secure the correct operation, the computer system can do nothing but set the frequency of the clock CLK provided to each block as the frequency by which the critical path is correctly executed by the EXB7. This means that the highest clock frequency is limited up to the frequency by which the severest case of the critical path can be processed correctly. How often the critical path is caused depends on the data to be actually processed in the computer system. However, in the most cases, the incidence of the critical path is assumed to be low enough so that almost all of the processing assumed to be actually processed is executed in a shorter execution time and is finished within the clock period correctly, or the critical path is not generated in the actual processing as a result. However, in these cases, when the possibility of the critical path occurrence should be considered, the clock cycle is not permitted to be shortened, so improved processing performance of the computer system cannot be achieved. Therefore, with the foregoing in mind, it is an object of the present invention to provide a computer system in which the pipeline is operated at the clock frequency higher than the clock frequency by which the critical path can be executed correctly, and to provide a computer system which can improve the processing performance and secure the correct operation for the critical path.